1. Field of Art
This disclosure relates to the field of system level modeling simulation, for example, SYSTEMC simulation.
2. Description of the Related Art
SYSTEMC is a system level modeling language used for simulating the behavior of a target system, such as a system on chip (SoC). SYSTEMC is approved by the Institute of Electrical and Electronics Engineers (IEEE) Standards Association as IEEE 1666. SYSTEMC allows a system to be described at different levels of abstraction. More specifically, SYSTEMC is a language built in standard C++ by extending the C++ language with the use of class libraries. SYSTEMC addresses the need for a system design and verification language that spans hardware and software. The language is particularly suited to modeling a system's partitioning, to evaluating and verifying the assignment of blocks to either hardware or software implementations, and to architect and measure the interactions between and among functional blocks.
In particular, IEEE Standard (Std.) 1666-2011, Clause 4.2.1.2, third paragraph provides that when the same target system is simulated multiple times using the same stimulus and the same version of the simulator, the SYSTEMC process ordering between different runs should not vary. That is, the execution order of SYSTEMC processes should be reproducible between various runs of the simulation of the target system in order that intermediate and end results are consistent and reproducible from run to run.
Typically, implementation of SYSTEMC simulations is performed in a single-threaded manner. However, the speed of the simulation has suffered when simulating target systems that themselves comprise multiple processor cores. For example, smart phones from year to year are increasingly faster and hold more computation power, and are designed with multiple processor cores for performing various tasks. As a result, the speed of a SYSTEMC simulation on a single processor core further and further lags behind the speed of the actual hardware device that is being simulated.
In order to speed up the implementation of SYSTEMC simulators, the simulation itself may be performed in a multi-threaded manner on a multi-core processing host system that comprises two or more processor cores within a single computing component. For example, multiple processor cores may be placed in a single processor die. Each of the processor cores is configured to act individually for purposes of program instructions. In that manner, by distributing instructions of a program for execution by the multiple processor cores, the speed for executing the program can be greatly increased when compared to executing the program on a single processor core. In particular, one way to speed up a SYSTEMC simulation is by executing multiple runnable SYSTEMC processes concurrently by means of multiple operating system (OS) threads.
However, SYSTEMC by itself is not multi-thread safe, and under IEEE Std. 1666-2011, a reproducible process execution order must be complied with. That is, the reproducibility of the SYSTEMC simulation (SYSTEMC kernel code as well as user code) should be multi-thread safe (MT safe). As such, data races (e.g., simultaneous accesses to shared resources) and other conditions that can affect the reproducibility of a SYSTEMC simulation from one run to the next must be avoided.
A conventional solution for multi-thread safeness is to guard accesses to shared resources with synchronization elements, such as OS mutexes. However, this is costly from a simulation performance perspective. Moreover, this approach by itself does not address SYSTEMC process execution order reproducibility in order to be compliant with the IEEE Std. 1666-2011 standard. It is thus desirable to have a SYSTEMC simulation that is reproducible and MT safe.